Low-noise amplifiers for integrated multi-mode direct-conversion receivers

The evolution of wireless telecommunication systems during the last decade has been rapid. During this time the design driver has shifted towards fast data applications instead of speech. In addition, the different systems may have a limited coverage, for example, limited to urban areas only. Thus, it has become important for a mobile terminal to be able to use different wireless systems, depending on the application chosen and the location of the terminal. The choice of receiver architecture affects the performance, size, and cost of the receiver. The superheterodyne receiver has hitherto been the dominant radio architecture, because of its good sensitivity and selectivity. However, superheterodyne receivers require expensive filters, which, with the existing technologies, cannot be integrated on the same chip as the receiver. Therefore, architectures using a minimum number of external components, such as direct conversion, have become popular. In addition, compared to the superheterodyne architecture, the direct-conversion architecture has benefits when multi-mode receivers, which are described in this thesis, are being designed. In this thesis, the limitations placed on the analog receiver by different system specifications are introduced. The estimations for the LNA specifications are derived from these specifications. In addition, the limitations imposed by different types of receiver architectures are described. The inductively-degenerated LNA is the basis for all the experimental circuits. The different components for this configuration are analyzed and compared to other commonly-used configurations in order to justify the use of an inductively-degenerated LNA. Furthermore, the design issues concerning the LNA-mixer interface in direct-conversion receivers are analyzed. Without knowing these limitations, it becomes difficult to understand the choices made in the experimental circuits. One of the key parts of this thesis describes the design and implementation of a single-chip multi-mode LNA, which is one of the key blocks in multi-mode receivers. The multi-mode structures in this thesis were developed for a direct-conversion receiver where only one system is activated at a time. The LNA interfaces to a pre-select filter and mixers and the different LNA components are analyzed in detail. Furthermore, the design issues related to possible interference from additional systems on single-chip receivers are analyzed and demonstrated. A typical receiver includes variable gain, which can be implemented both in the analog baseband and/or in the RF. If the variable gain is implemented in the RF parts, it is typically placed in the LNA or in a separate gain control stage. Several methods that can be used to implement a variable gain in the LNA are introduced and compared to each other. Furthermore, several of these methods are included in the experimental circuits. The last part of this thesis concentrates on four experimental circuits, which are described in this thesis. The first two chips describe an RF front-end and a direct-conversion receiver for WCDMA applications. The whole receiver demonstrates that it is possible to implement A/D converters on the same chip as sensitive RF blocks without significantly degrading receiver performance. The other two chips describe an RF front-end for WCDMA and GSM900 applications and a direct-conversion receiver for GSM900, DCS1800, PCS1900 and WCDMA systems. These ICs demonstrate the usability of the circuit structure developed and presented in this thesis. The chip area in the last multi-mode receiver is not significantly increased compared to corresponding single-system receivers.reviewe

Routed end-to-end Ethernet : Proof of Concept

Tämän diplomityön tavoitteena on tutkia ja analysoida Ethernet- ja IEEE 802.1 -standardeja, sekä IPv4- ja IPv6-protokollia. Näiden parhaita puolia yhdistämällä kehitettiin uusi päästä-päähän reitittävä Ethernet -konsepti, jonka mukaan rakennettiin Proof of Concept -verkko. Tämä idea pyrkii ratkaisemaan Internetin suurimman ongelman, jossa osoiteavaruudesta loppuvat osoitteet, käyttämällä laitteiden identifioimiseen ja Ethernet-pakettien reitittämiseen sekä MAC- että NSAP-osoitteita. Hierarkkisuuden puute osoitteissa estää tehokkaan reitityksen ja sen takia Ethernet-verkot eivät skaalaudu maailmanlaajuiseksi verkoksi. IEEE 802.1 -standardeissa on parannettu Ethernet-verkkojen skaalautuvuutta, mutta osoitteistusta ei ole muutettu ja reititykseen käytetään edelleen Spanning Tree -protokollaa. Internet-protokollan versio 4:stä tuli Internetin hallitseva verkkoprotokolla, koska siinä osoitteisto on hierarkkinen, mikä mahdollistaa tehokkaan reitityksen. Ongelmaksi on kuitenkin muodostunut pieni osoiteavaruus, josta osoitteet alkavat loppua. IPv6:ssa on suurempi osoiteavaruus, mutta siltikään se ei ole syrjäyttänyt IPv4-osoitteita. RE2EE:n ideana on lisätä Ethernet-verkkoon hierarkkiset osoitteet, jotka yhdessä mahdollistaisivat riittävän ison osoiteavaruuden ja tehokkaan reitityksen. Proof of Conceptissa luotiin RE2EE-verkko pienessä mittakaavassa ja todistettiin sen avulla RE2EE:n perusominaisuuksin toteuttaminen käyttämällä ainoastaan Ethernet-paketteja.The main goal of this thesis is to investigate and analyse the Ethernet and IEEE 802.1 standards, and IPv4 and IPv6 protocols. From those combine a new idea of Routed End-to-End Ethernet in theory and to build a Proof of Concept network that shows it in a small scale. This concept would solve the address exhaustion problem by using MAC and NSAP addresses for host identification and for routing Ethernet packets in the network. From Ethernet and IEEE 802.1 standards we found that the main problem of the Ethernet is that it does not have hierarchical addresses. Hierarchical addresses would allow efficient routing enabling the network to scale globally. IEEE 802.1 has many standards with features for scaling Ethernet networks better, but they are still not enough. The only routing protocols used in the Ethernet networks are still the Spanning Tree Protocols. Internet Protocol version 4 that is the dominant network protocol in the Internet, has a hierarchical address space enabling efficient routing. A big problem with IPv4 is that the address space is small and is running out of addresses. IPv6 has larger address space, but for some reason the deployment is really slow. RE2EE would use Ethernet added with hierarchical addresses for the Internet. This would make the address space large enough and also efficient routing would be possible. In the Proof of Concept a small scale network was built, which showed that it is possible to create the basic functionalities of RE2EE using only Ethernet packets

Adaptive Nonlinear RF Cancellation for Improved Isolation in Simultaneous Transmit-Receive Systems

This paper proposes an active radio frequency (RF) cancellation solution to suppress the transmitter (TX) passband leakage signal in radio transceivers supporting simultaneous transmission and reception. The proposed technique is based on creating an opposite-phase baseband equivalent replica of the TX leakage signal in the transceiver digital front-end through adaptive nonlinear filtering of the known transmit data, to facilitate highly accurate cancellation under a nonlinear TX power amplifier (PA). The active RF cancellation is then accomplished by employing an auxiliary transmitter chain, to generate the actual RF cancellation signal, and combining it with the received signal at the receiver (RX) low noise amplifier (LNA) input. A closed-loop parameter learning approach, based on the decorrelation principle, is also developed to efficiently estimate the coefficients of the nonlinear cancellation filter in the presence of a nonlinear TX PA with memory, finite passive isolation, and a nonlinear RX LNA. The performance of the proposed cancellation technique is evaluated through comprehensive RF measurements adopting commercial LTE-Advanced transceiver hardware components. The results show that the proposed technique can provide an additional suppression of up to 54 dB for the TX passband leakage signal at the RX LNA input, even at considerably high transmit power levels and with wide transmission bandwidths. Such novel cancellation solution can therefore substantially improve the TX-RX isolation, hence reducing the requirements on passive isolation and RF component linearity, as well as increasing the efficiency and flexibility of the RF spectrum use in the emerging 5G radio networks.Comment: accepted to IEE

Full-Duplex OFDM Radar With LTE and 5G NR Waveforms: Challenges, Solutions, and Measurements

This paper studies the processing principles, implementation challenges, and performance of OFDM-based radars, with particular focus on the fourth-generation Long-Term Evolution (LTE) and fifth-generation (5G) New Radio (NR) mobile networks' base stations and their utilization for radar/sensing purposes. First, we address the problem stemming from the unused subcarriers within the LTE and NR transmit signal passbands, and their impact on frequency-domain radar processing. Particularly, we formulate and adopt a computationally efficient interpolation approach to mitigate the effects of such empty subcarriers in the radar processing. We evaluate the target detection and the corresponding range and velocity estimation performance through computer simulations, and show that high-quality target detection as well as high-precision range and velocity estimation can be achieved. Especially 5G NR waveforms, through their impressive channel bandwidths and configurable subcarrier spacing, are shown to provide very good radar/sensing performance. Then, a fundamental implementation challenge of transmitter-receiver (TX-RX) isolation in OFDM radars is addressed, with specific emphasis on shared-antenna cases, where the TX-RX isolation challenges are the largest. It is confirmed that from the OFDM radar processing perspective, limited TX-RX isolation is primarily a concern in detection of static targets while moving targets are inherently more robust to transmitter self-interference. Properly tailored analog/RF and digital self-interference cancellation solutions for OFDM radars are also described and implemented, and shown through RF measurements to be key technical ingredients for practical deployments, particularly from static and slowly moving targets' point of view.Comment: Paper accepted by IEEE Transactions on Microwave Theory and Technique

A 0.9-Nyquist-Band Digital Timing Mismatch Correction for Time-Interleaved ADCs Achieving Delay Tuning Range of 0.12-Sample-Period

Time-interleaved analog-to-digital converters (TIADC) require channel matching in terms of offset, gain, and sampling clock skew to achieve best data conversion performance. Conventionally, correction of skew mismatch is realized with analog delay lines, making it challenging for high-speed ADC designs to achieve fine delay resolution over wide tuning range while maintaining low clock jitter. Digital skew correction allows greater flexibility than analog solutions, but is hindered by a significant hardware footprint. This paper demonstrates digital filter-based timing skew correction approach suitable for on-chip implementation. In a 10-bit 8-channel TI-ADC the proposed structure corrects mismatch magnitudes up to 0.12 sample period across 0.9 Nyquist band while requiring only 65% hardware of similar architectures of equivalent performance. The presented digital circuit uses reduced combinational paths and operates at a clock rate of single ADC channel, making it applicable for digitally-assisted high-speed TI-ADCs.acceptedVersionPeer reviewe

Design of Cyclic-Coupled Ring Oscillators with Guaranteed Maximal Phase Resolution

Cyclic-coupled ring oscillators (CCRO), which consist of M ring oscillators each with N inverting stages, can be used in time-domain data converters to achieve sub-gate-delay resolution and improved phase noise performance compared to a single ring oscillator (RO). However, CCROs can oscillate in several different oscillation modes, where some modes contain overlapping phases. Such in-phase oscillations severely degrade the performance of a time-domain data converter by undermining the sub-gate-delay of the CCRO. This paper presents a design method to avoid the undesired in-phase oscillation modes, and thus achieve guaranteed maximal phase resolution regardless of the oscillation mode, by properly selecting the CCRO dimensions N and M. We show, both theoretically and with transistor-level simulations, that mode-agnostic maximum phase resolution can be ensured by selecting a prime M together with an N which is co-prime with M.acceptedVersionPeer reviewe

Fully Digital On-Chip Wideband Background Calibration for Channel Mismatches in Time-Interleaved Time-Based ADCs

This letter presents a fully integrated on-chip digital mismatch compensation system for time-based time-interleaved (TI) data converters. The proposed digital compensation features blind calibration of gain, offset, and timing mismatches. The implemented system uses time-based sampling clock mismatch detection, achieving convergence within 32K samples, which is on par with analog-assisted background methods. A specialized filter structure compensates for timing mismatches of magnitude up to 0.21 of the sampling period, nearly triple the range of other published digital compensation methods, and is effective for input signals up to 0.92 Nyquist bandwidth. The on-chip digital correction achieves suppression of all mismatch tones to levels below −60 dBc while running fully in the background. The operation is demonstrated with an 8× TI 2-GS/s analog-to-digital converter (ADC) prototype chip implemented in a 28-nm CMOS process.publishedVersionPeer reviewe

Genome-wide landscape of liver X receptor chromatin binding and gene regulation in human macrophages

<p>Abstract</p> <p>Background</p> <p>The liver X receptors (LXRs) are oxysterol sensing nuclear receptors with multiple effects on metabolism and immune cells. However, the complete genome-wide cistrome of LXR in cells of human origin has not yet been provided.</p> <p>Results</p> <p>We performed ChIP-seq in phorbol myristate acetate-differentiated THP-1 cells (macrophage-type) after stimulation with the potent synthetic LXR ligand T0901317 (T09). Microarray gene expression analysis was performed in the same cellular model. We identified 1357 genome-wide LXR locations (FDR < 1%), of which 526 were observed after T09 treatment. <it>De novo </it>analysis of LXR binding sequences identified a DR4-type element as the major motif. On mRNA level T09 up-regulated 1258 genes and repressed 455 genes. Our results show that LXR actions are focused on 112 genomic regions that contain up to 11 T09 target genes per region under the control of highly stringent LXR binding sites with individual constellations for each region. We could confirm that LXR controls lipid metabolism and transport and observed a strong association with apoptosis-related functions.</p> <p>Conclusions</p> <p>This first report on genome-wide binding of LXR in a human cell line provides new insights into the transcriptional network of LXR and its target genes with their link to physiological processes, such as apoptosis.</p> <p>The gene expression microarray and sequence data have been submitted collectively to the NCBI Gene Expression Omnibus <url>http://www.ncbi.nlm.nih.gov/geo</url> under accession number GSE28319.</p

Energy-Efficient Cyclic-Coupled Ring Oscillator With Delay-Based Injection Locking

This brief presents a new tristate-based delay cell to realize the recently proposed delay-based injection locking in ring oscillators. The circuit is then applied to implement a cyclic-coupled ring oscillator (CCRO). Compared to an inverter-based CCRO with multi-drive injection, the proposed circuit eliminates the static short-circuit current drawn from the supply when drive circuits are in conflicting logic states, thus reducing the power consumption of the CCRO. The functionality and improved energy efficiency of the proposed circuit is demonstrated with circuit simulations of a CCRO implemented in a 28-nm CMOS process. The CCRO employing the proposed technique achieves up to 25% lower power consumption and over 20% lower power-delay product (PDP) compared to the inverter-based CCRO.This brief presents a new tristate-based delay cell to realize the recently proposed delay-based injection locking in ring oscillators. The circuit is then applied to implement a cyclic-coupled ring oscillator (CCRO). Compared to an inverter-based CCRO with multi-drive injection, the proposed circuit eliminates the static short-circuit current drawn from the supply when drive circuits are in conflicting logic states, thus reducing the power consumption of the CCRO. The functionality and improved energy efficiency of the proposed circuit is demonstrated with circuit simulations of a CCRO implemented in a 28-nm CMOS process. The CCRO employing the proposed technique achieves up to 25% lower power consumption and over 20% lower power-delay product (PDP) compared to the inverter-based CCRO.publishedVersionPeer reviewe